職位描述
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職位描述:
responsibilities:
1. responsible for technical management for team and leading team to finish be tasks.
2. work as technical expert to support technical team.
3. responsible for developing digital designs with emphasis on backend, including floor-plan, power planning, place, cts and route.
4. work with front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis
5. optimization and verification of layout for tape-out (including rc extraction, eco, drc, lvs).
6. power ir drop analysis and optimization, area and parasitic layout optimization, chip size optimization.
7. static timing analysis (prime time) and setup/hold fix.
8. formal verification for equivalence checking (formality).
9. generation of fill structures according to technology requirements.
requirements:
1. 1-3 years experience for technical team leadership.
2. about 5 years experience in backend design flow (apr) with proven soc tape-out experience.
3. experienced in synopsys/cadence automatically physical implementation tools and flows (ic-compiler/ astro / soc-encounter/ milky-way/ star-rcx) is a plus.
4. experience with one or more scripting languages (perl, tcl, or shell) to make reusable automatically flow is a plus.
5. experience and knowledge about fe design (rtl code, flow) and verification is a plus.
6. good communication in teamwork spirit.
7. good analytical and debugging skills.
8. good command of english.
responsibilities:
1. responsible for technical management for team and leading team to finish be tasks.
2. work as technical expert to support technical team.
3. responsible for developing digital designs with emphasis on backend, including floor-plan, power planning, place, cts and route.
4. work with front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis
5. optimization and verification of layout for tape-out (including rc extraction, eco, drc, lvs).
6. power ir drop analysis and optimization, area and parasitic layout optimization, chip size optimization.
7. static timing analysis (prime time) and setup/hold fix.
8. formal verification for equivalence checking (formality).
9. generation of fill structures according to technology requirements.
requirements:
1. 1-3 years experience for technical team leadership.
2. about 5 years experience in backend design flow (apr) with proven soc tape-out experience.
3. experienced in synopsys/cadence automatically physical implementation tools and flows (ic-compiler/ astro / soc-encounter/ milky-way/ star-rcx) is a plus.
4. experience with one or more scripting languages (perl, tcl, or shell) to make reusable automatically flow is a plus.
5. experience and knowledge about fe design (rtl code, flow) and verification is a plus.
6. good communication in teamwork spirit.
7. good analytical and debugging skills.
8. good command of english.
工作地點
地址:西安雁塔區西安-科技二路
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詳細位置,可以參考上方地址信息
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職位發布者
HR
西安紫光國芯半導體有限公司
-
電子技術·半導體·集成電路
-
200-499人
-
公司性質未知
-
陜西省西安市高新6路38號騰飛創新中心a座4層

5年以上
碩士
最近更新
3798人關注
注:聯系我時,請說是在河北人才網上看到的。
